Timing Closure Requires Up-Front Work By Ted Williams Successful timing achieved on first silicon Download a PDF of this article

Fault Coverage Vies for Clear DFT Rules By Luke L. Chang Part 2 of a two-part discussion of full-scan testing Download a PDF of this article Hybrid Architecture Takes Digital Picture By Jeffery M. Arnold and Neal Stollon SoC components are applied to digital still photography Download a PDF of this article Converting FPGAs to ASICS for SoC Designs By Vince Hopkins Download a PDF of this article Self-Repair Boosts Memory SoC Yields By Vincent Ratford Algorithim vastly improves SoC yields Download a PDF of this article New Models Sought for Less Than 0.13 Micron By Xisheng Zhang and Mark C. Williams Deep-submicron designs require different modeling Download a PDF of this article

Editorial By Ron Wilson Timing's everything, everything's timed Download a PDF of this article Working Papers By Warren Miller, Peter Kwan and Kent Narveson FPGA designs need timing closure path Download a PDF of this article Viewpoint By Sean Dart Integrate tools for effective verification Download a PDF of this article

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